![]() The simulator receives the taskgraph file and protocol type as specified by the user as its input. Then, operations from this queue are popped and executed whenever the previous operation finishes. Once a task appears on a context’s taskQueue, the processor parses that task to form a queue of read/write operations. As each task finishes, it assigns those successors of that task whose all ancestor tasks have finished to the assigned context. The simulator takes as input the taskgraph of the program and generates as many contexts (rounded down to a power of 2 for simplicity) as in the taskgraph. Additionally, each task has a collection of memory reads and writes which is used by the simulator to simulate the behavior of a directory-based coherence scheme. A taskgraph is a graph of tasks carried out by the program where each task is performed by one thread or core. Brian Railing to generate taskgraphs of programs we wished to simulate. We hope that our project would eventually come available as a tool for programmers who are interested in knowing the cache behavior and memory reference characteristics of their programs, which could potentially be helpful in optimizing the code. Therefore, we decide to develop a deeper understanding of the various directory-based cache coherence protocols by actually implementing them and observe cache behavior of programs with distinct memory traces. ![]() Comparing to snooping-based which relies heavily on broadcasting on the entire bus, directory-based protocols seems to be more scalable with regard to number of processors as it allows point-to-point communication. In the lectures, we discussed both snooping-based and directory-based cache coherence protocols. MotivationĬache coherence is one of the most important topics in designing multi-processor caches. ![]() It’s biggest strength is that it is highly scalable as cores only talk to cores they are interested in instead of broadcasting the message across the entire interconnect. Each core is connected to a directory that keeps track of state of cache lines in the core’s’ local memory vs using a bus as in a snooping based scheme. ![]() It takes in memory reference traces, simulates cache and directory traffic, and finally analyzes/reports the behaviors.Ī Directory-Based Cache Coherence Scheme solves the cache coherence problem in Distributed Shared Memory or NUMA systems. SyncdSim is a directory-based cache coherence simulator that supports MSI and MESI (more to come). Strauss K, Shen X, Torrellas J (2007) Uncorq: unconstrained snoop request delivery in embedded-ring multiprocessors.SyncdSim SyncdSim Be coherent, be cool. In: Proceedings of the 30th annual international symposium on computer architecture international symposium on computer architecture, San Diego, 9–11 June 2003 Martin M, Hill M, Wood D (2003) Token coherence: decoupling performance and corrections. IBM J Res Dev 46(1):5Ĭhaiken D, Fields C, Kurihara K, Agarwal A (1990) Directory-based cache coherence in large-scale multiprocessors. Tendler J, Dodson J, Fields J, Le H, Sinharoy B (2002) POWER-4 system microarchitecture. Gniady C, Falsafi B, Vijaykumar T (1999) Is SC+ILP=RC? In: Proceedings of the 26th annual international symposium on computer architecture (ISCA 1999), Atlanta, 2–, pp 162–17 Intel Corporation (1999) IA-64 application developer’s architecture guide May C, Silha E, Simpson R, Warren H (1994) The powerPC architecture: a specification for a new family of RISC processors. Lamport L (1979) How to make a multiprocessor computer that correctly executes multiprocess programs.
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